SIMM slot order in Sun IPX
2007-12-25 8:19:00
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I have received replies from many people - too numerous to thank each
and every one individually. So this is to thank the following people
who responded (and to the others who may yet do so while this summary
is on the way):
"Chris P. Ross" <cross@eng.umd.edu>
cc_koper@rcvie.co.at (Koper Zangocyan)
eedbew@teamos.ericsson.se (Bernhard Weinelt)
tkevans@eplrx7.es.duPont.com (Tim Evans)
davis%opus@uunet.UU.NET (Thomas J Davis)
twhitely@tr1072.to.ford.com (Ted Whitely)
archer!banshee!myk@uunet.UU.NET (Mike Steadman)
danny@ews7.dseg.ti.com (Danny Johnson)
poffen@sj.ate.slb.com (Russ Poffenberger)
"Andrew S. Rogers" <arogers@eng.umd.edu>
jperry@gandalf.srl.ford.com (Jon C. Perry)
steve@seattle.avcom.com (Steve Lee)
oliver@ast.saic.com (Thomas W Oliver)
bagate!blazer.babss.basg.com!tkw (Terry White)
dgreen@astro.ge.com (David Green)
mayb@saifr00.cfsat.honeywell.com (Bill May)
Shane.Sigler@Corp.Sun.COM (Shane Sigler)
Rich Schultz <rich@ccrwest.org>
Samir Taylor <cadskt@mto.det.cad.gmeds.com>
Gary Marazita (Melbourne Aust. Eng. ) <GAM.GARY@MELPN1.CV.COM>
Original message:
----------------
This was my original mail message:
> Hi, all!
>
> Could someone please tell me the correct SIMM slot order for two 16MB
> SIMM's in a Sun IPX?
>
> One Sun document says that these should be in slot 1 and 2; another
> insists they should be in 1 and 3 (assuming that the slots are labelled
> 1 through 4 for the purpose of this mail message).
>
> Can someone confirm which is correct? And why?
>
> Please, and Thanks.
>
> Z
Summary:
---------
Since the slots are generally labelled 0, 1, 2, and 3, (from front of
cabinet to back) rather than the brain-damaged way I had it, let me use
that as the method for summarizing.
The general consensus was that the correct SIMM order was 0, 2, 1, 3.
This was supported by the Sun Field Engineer Handbook (dated 1/15/92)
that I also got a chance to look at. One person recommended that I buy
a copy of this (and updates), but I also found out just how expensive
it is! Sorry, Sun, no way! I'd rather buy an external 1.0GB disk drive
for my machine for *that* amount of money! :-)
Three people suggested that the correct order is 0, 1, 2, 3, but one of
them referenced the same Sun document that I saw state it this way, so
this document may be in error (old Sun IPX installation manual). One
of these persons also felt that it may not matter anyway.
Four people suggested that the order does or may not matter, but one of
them suggested that the boot prom may not have any problem seeing and
testing it this way, but the kernel will not see it (turned out to be
erroneous - the kernel will see it; see later).
Other Comments:
--------------
1. Quite a few people recommend that I make sure that slot 0 was
filled. That is true - all three of my Sun references show that to be
necessary for the machine to pass its power-on tests and boot.
2. The memory order for varying size SIMM's (i.e. if I had any 4Mb
SIMM's as well), is to make sure that the smaller sizes are always in
"later" slots.
3. It is also important to make sure that slot 0 is a 16MB SIMM if
mixed sizes; this is effectively required by the previous statement.
However, one person said that they had violated this "rule" with no
problems, and they did not know why it worked fine!
Reasons:
-------
No-one had a *concrete* suggestion as to why this is order is or may be
important. One person stated that the memory simm order is now
staggered (instead of straight arrangement) in the IPX, Sparc2 and
Sparc10. Another suggested that this is because of the way it was done
in earlier machines, and has become a defacto standard.
I guess the bottom line is no-one *really* knows the reason as to why
this needs to be done in the IPX. I would have guessed refresh cycle
addressing reasons, but this would be more significant on 16 bit bus
machines. No-one supported this theory.
The Bottom Line:
---------------
Since the majority of people recommended 0, 2, 1, 3, that is what I
will use. For a lark, I tried 0, 1, 2, 3 (well, 0 and 1, since I only
have two SIMM's) and it worked fine anyway! The boot prom saw it and
the kernel recognized the extra memory as well. I did not see any
perceptible speed differences or anything untoward (no rigorous
testing though), so the bottom line is that it probably does not
matter. I will still follow the general recommendation anyway for
consistency.
Comments
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